OpenBSD cvs log

created 2018-11-30T00:16:30Z
begin 2018-07-24T00:00:00Z
end 2018-07-25T00:00:00Z
path src/sys
commits 10

date 2018-07-24T02:42:25Z
author guenther
files src/sys/arch/amd64/amd64/locore.S log diff annotate
src/sys/arch/amd64/amd64/vector.S log diff annotate
src/sys/arch/amd64/amd64/vmm_support.S log diff annotate
src/sys/arch/amd64/include/asm.h log diff annotate
src/sys/arch/amd64/include/cpufunc.h log diff annotate
message Also do RSB refilling when context switching, after vmexits, and
when vmlaunch or vmresume fails.

Follow the lead of clang and the intel recommendation and do an lfence
after the pause in the speculation-stop path for retpoline, RSB refill,
and meltover ASM bits.

ok kettenis@ deraadt@

date 2018-07-24T07:40:35Z
author yasuoka
files src/sys/net/if_gre.c log diff annotate
message When a GRE packet goes to "decline", the mbuf pointer was not updated
properly. This had caused an panic when the mbuf pointer is updated.
Found by IIJ.

ok dlg

date 2018-07-24T14:49:44Z
author guenther
files src/sys/arch/amd64/include/cpufunc.h log diff annotate
message Fix previous commit: the RSB refill bits change %rcx so it needed to be
given an input/output ASM constraint...but I made it output-only, so the
compiler deleted the initialization.

reported by many, starting with Edd Barrett (edd(at)

date 2018-07-24T15:45:52Z
author kettenis
files src/sys/dev/sdmmc/if_bwfm_sdio.c log diff annotate
message Add support fotr the BCM4335/4339 SDIO chip to bwfm(4). This one is a bit
slow booting up, so give it a bit longer to enable the clock.

ok patrick@

date 2018-07-24T16:11:33Z
author patrick
files src/sys/dev/fdt/sxitwi.c log diff annotate
message The I2C controller on the Allwinner hardware is actually a modified
Marvell controller. The difference is essentially register offsets
and a clock divider calculation based on a power of two. Also this
particular hardware needs a delay after sending a stop and before
reading the status register since apparently the data doesn't
propagate fast enough. This makes sxitwi(4) work on the Marvell
Armada 38x.

ok kettenis@

date 2018-07-24T17:31:23Z
author brynet
files src/sys/arch/i386/i386/machdep.c log diff annotate
src/sys/arch/i386/include/specialreg.h log diff annotate
message Do the same for i386 as amd64:

Add "Mitigation G-2" per AMD's Whitepaper "Software Techniques for
Managing Speculation on AMD Processors"

By setting MSR C001_1029[1]=1, LFENCE becomes a dispatch serializing

ok deraadt@

date 2018-07-24T21:16:59Z
author kettenis
files src/sys/dev/pci/pcidevs log diff annotate
message Add SanDisk/WD Black NVMe devices.

From Bryan Vyhmeister

date 2018-07-24T21:17:25Z
author kettenis
files src/sys/dev/pci/pcidevs.h log diff annotate
src/sys/dev/pci/pcidevs_data.h log diff annotate
message regen

date 2018-07-24T21:52:38Z
author kettenis
files src/sys/dev/fdt/mvclock.c log diff annotate
message Add clock needed to support the i2c controllers on the Marvell ARMADA 7K/8K.

ok patrick@

date 2018-07-24T21:53:46Z
author kettenis
files src/sys/dev/fdt/sxitwi.c log diff annotate
message Add support for the i2c controller on the Marvell ARMADA 7K/8K SoC as well.

ok patrick@